We are looking for a skilled and motivated DV Engineer to join our subsystem verification team. In this role, you will be responsible for the functional verification of complex IPs and subsystems that form the building blocks of our next-generation SoCs. You will work closely with design, architecture, and SoC integration teams to define verification strategies, build robust testbenches, and drive coverage closure to deliver high-quality silicon.
Minimum Qualifications:
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
Key Responsibilities
Own and drive functional verification of IPs and subsystems from planning through sign-off.
Develop verification plans, testbench architecture, and test cases based on design and architecture specifications.
Build and enhance reusable, scalable verification environments using System Verilog and UVM.
Develop and maintain constrained-random and directed test scenarios, assertions, and functional coverage models.
Drive coverage closure (code + functional) and debug failures using waveform/log analysis.
Collaborate with design, architecture, and SoC integration teams to resolve issues and ensure verification completeness.
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Contribute to regression setup, triage, and maintenance to ensure verification quality and throughput.
Support IP-to-subsystem-to-SoC integration and reuse of verification collateral across levels.
Required Qualifications
4–6 years of hands-on experience in ASIC/SoC functional verification.
Strong proficiency in System Verilog and UVM methodology.
Proven experience in IP, subsystem, and/or SoC-level verification.
Solid understanding of verification concepts: constrained-random stimulus, functional coverage, assertions (SVA), and scoreboarding.
Strong debug skills using simulation logs and waveform tools (e.g., Verdi/FSDB).
Good understanding of digital design fundamentals, bus protocols, and SoC architecture.
Proficiency in scripting (Python/Perl/Tcl) for automation and flow development.
Strong analytical, problem-solving, and communication skills.
Preferred / Good-to-Have Skills
Experience with low-power verification (UPF/Power-aware) flows.
Exposure to Gate-Level Simulation (GLS) including timing and SDF-based verification.
Familiarity with formal verification, emulation, or performance verification.
Experience with industry-standard bus protocols (AXI/AHB/APB, etc.).
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