Staff Digital Design Engineer
NXP Semiconductors
Role Summary
We are seeking a Senior Lead Digital Designer to lead the architecture, implementation, and integration of digital subsystems for Automotive Ethernet PHY products (10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, and multi‑gig automotive SerDes technologies).
The role involves driving digital micro-architecture, state machines, PCS functionality, safety mechanisms, and end‑to‑end digital design across the PHY.
Key Responsibilities
- Architecture & Technical Leadership
- Define and own digital subsystem micro‑architecture for Automotive Ethernet PHYs, including:
- PCS pipelines and encoding/decoding logic
- Scramblers/descramblers, CRC engines, alignment & framing
- Packet processing, link monitoring, error handling
- Interface logic (MII, RMII, RGMII, GMII, XGMII depending on product line)
- Processor based SoC design
- Perform system‑level partitioning between digital, analog/mixed-signal, and firmware components.
- Lead feasibility studies, power/performance trade-offs, and digital architecture exploration.
- RTL Design & Implementation
- Develop high-quality RTL (Verilog/SystemVerilog) for control, datapath, and protocol logic.
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Drive digital front-end flows including:
- Lint, CDC/RDC, reset architecture, synthesis guidance
- Timing constraints and logic optimization
- Work with DV to define coverage goals, corner cases, and feature verification plans.
- System‑Level Ownership
- Translate system requirements, IEEE 802.3 specifications, and architecture documents into robust digital designs.
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