Principal Engineer- Design Verification

Company Description

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

Job Summary:

We are seeking a highly experienced Verification Lead to drive the verification strategy and execution for next-generation UA Link Switch products within the Memory Interface Division (MID). The candidate will be responsible for leading verification efforts across complex digital subsystems and SoCs, ensuring first-silicon success for high-performance, high-bandwidth interconnect and switching solutions.

The ideal candidate will possess deep expertise in modern verification methodologies and extensive experience verifying large-scale, high-speed digital designs involving switching fabrics, SerDes-based interfaces, memory subsystems, and complex SoC architectures.

Key Responsibilities

• Define and own the verification strategy, methodology, and execution plan for UA Link Switch products.

• Lead verification architecture, testbench development, coverage planning, and verification closure activities.

• Build and drive scalable UVM/ System Verilog-based verification environments for complex SoC and subsystem designs.