Digital Design Engineer, RTL IP, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 4 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages, such as Verilog or SystemVerilog.

• Experience with bus protocols such as Advanced Extensible Interface (AXI), Coherent Hub Interface (CHI), AXI Coherency Extensions (ACE) Lite.

• Experience with multiple SoCs with silicon success and with chip design flow.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.

• Experience in micro-architecture and coding in one or more of these areas: memory compression, interconnects, coherence, cache.

• Experience working with the internals of Network-on-Chip (NoC).

• Domain knowledge and expertise with ARM based SoC, Debug (e.g., coresight).

• Understanding of cross-domain involving domain validation, design for testing, physical design, and software.

• Proficiency with Application-Specific Integrated Circuit (ASIC) design methodologies for front quality checks like; Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation.