Staff Physical Design Engineer
Silicon Labs
Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.
Meet the Team Join a dynamic Physical Design team that drives end-to-end SoC implementation, from RTL to tape-out. We work closely with design, verification, and architecture groups to deliver high-performance, low-power solutions. Collaboration, innovation, and technical excellence define our culture—making this an exciting place to grow, lead, and make a real impact.
About the Role
We are seeking a highly skilled Physical Design to join our Silicon Engineering team in Hyderabad. In this role, you will drive the design, implementation, and optimization of advanced SoCs using state-of-the-art physical design methodologies. You will work on challenging synthesis, floorplanning, place-and-route, timing closure, and sign-off flows while mentoring a team of engineers and collaborating with cross-functional groups. This is an excellent opportunity to contribute to world-class silicon solutions and grow as a technical leader.
Responsibilities
- Lead and execute the end-to-end physical design flow for complex SoCs and IP blocks (RTL handoff to GDSII).
- Define and drive strategies for floorplanning, CTS, placement, routing, and timing closure.
- Own and optimize PPA (Power, Performance, Area) metrics for assigned designs.
- Manage design constraints, synthesis strategies, and sign-off (timing, IR drop, EM, DRC/LVS).
- Collaborate with RTL, DFT, verification, and packaging teams for seamless integration.
- Drive EDA tool automation and methodology improvements for efficiency and scalability.
- Mentor and guide junior engineers to foster technical growth and excellence.
- Work with foundries and vendors on process bring-up, PDK updates, and tape-out readiness.
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