STA CAD Methodology Engineer, Sr Lead

Job Description

We are looking for a highly experienced STA/Timing CAD Methodology Lead to own, architect, and scale the next generation of static timing analysis methodologies for cutting‑edge, high‑performance SoC designs. In this role, you will be the technical force behind enabling robust STA flows, accelerating ECO convergence, and shaping the timing closure strategy for complex designs in advanced technology nodes.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Additional Job Description

What You Will Lead & Influence

As the STA CAD Methodology Lead, you will:

• Define, develop, and deploy industry‑leading STA and ECO methodologies across multiple design teams.

• Drive continuous innovation in timing flows, improving runtime, accuracy, and overall execution efficiency.

• Own end‑to‑end STA methodology, from constraints development to timing closure sign‑off.

• Collaborate closely with PNR, RTL, Extraction, and Technology teams to ensure smooth convergence at both block and top levels.

• Tackle complex timing challenges on advanced nodes to guarantee first‑time‑right tapeouts with exceptional quality.