Silicon Engineer, Design Verification

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 1 year of experience with creating/using verification components and environments in UVM methodology at IP or Subsystem level.

• Experience developing and maintaining design verification (DV) testbenches, test cases, and test environments.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience with image processing, computer vision or machine learning IPs.

• Experience with AMBA (APB/AXI/ACE) or other standard protocols.

• Familiarity with CPU, GPU or other computer architectures.