Senior Staff Engineer, Low Power & Formal Equivalence Verification (VCLP / FEV)

Company Description

Renesas is a global semiconductor leader shaping the backbone of next‑generation automotive, industrial, cloud, and IoT innovation. With over $9.3 billion in annual revenue (2024) and a world‑class team of 22,700+ employees, Renesas operates at scale while retaining the agility to drive category‑defining breakthroughs. The company’s footprint spans more than 30 countries, enabling deep customer proximity and a uniquely global innovative engine. As Japan’s semiconductor powerhouse and a top global player in microcontrollers, analog, and power technologies, Renesas delivers real‑world impact across EVs, smart factories, renewable energy infrastructure, and edge intelligence. For ambitious problem‑solvers who want to work on meaningful, systems‑level challenges with huge industry leverage, Renesas offers the scale, stability, and strategic clarity of a market leader—paired with the transformative momentum of a company reinventing how the world computes, connects, and electrifies.

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

Job Description

We are seeking a highly motivated and experienced engineer to lead Low Power (Power Intent) and Formal Equivalence Verification (FEV/LEC) activities for complex ASIC/SoC programs. The ideal candidate will be responsible for defining and signing off power intent (UPF/CPF), ensuring correct low-power implementation across all design stages, and driving formal equivalence verification from RTL through synthesis, DFT, implementation, and ECOs to tapeout.

This role requires close collaboration with Architecture, RTL, Verification, Synthesis, DFT, STA, Physical Design, PDN, and Signoff teams to ensure functional correctness, low-power integrity, and successful tapeout execution.

Key Responsibilities

Low Power / Power Intent