Senior Engineer - Physical Design

About this Opportunity

Join Ericsson's cutting-edge journey to shape the future of 5G networks! As a Physical Design Engineer, you'll work on pioneering digital ASIC designs vital to Ericsson's mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you're passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you.

At Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you'll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom!

We are hiring a Physical Design Engineer to own the physical implementation flow on high-performance, low-power SoC designs at advanced process nodes. Your primary focus will be die-level floorplanning, full-chip place-and-route, and timing-driven physical closure — while also contributing to synthesis and static timing analysis (STA) signoff as secondary responsibilities. You will work closely with RTL design, synthesis, DFT, and verification teams throughout the full design cycle from netlist hand-off to GDSII sign-off.

What you will do:

Floorplanning & Physical Implementation

• Own die-level and block-level floorplanning using Cadence Innovus or Synopsys ICC2 — defining die size, I/O ring placement, power ring topology, and macro placement strategies.

• Perform early floorplan exploration to evaluate area, aspect ratio, and pin assignment trade-offs in collaboration with the architecture and package teams.

• Plan and implement hierarchical design partitioning — define interface timing budgets, feedthrough corridors, and block-level pin constraints for clean top-level integration.

• Coordinate macro placement with memory compilers, analog IP, and hard macros; manage blockage and halo constraints to minimize routing congestion.