Senior Engineer-Low power verification
Ericsson
About this opportunity
Join our new ASIC top level verification team.
We specialize in the top-level verification of cutting-edge ASICs that power complex high-performance systems. Our designs are either monolithic ASICs or integrated multi-chip-modules holding several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe.
As an ASIC Top-Level Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security.
You will play an important role in the team developing environments and/or tests run in SystemC/TLM simulation, RTL environments, hardware emulation, and eventually on Silicon.
What you will do
Low power verification is a focus area, but as a senior verifier the person is expected to support in various types of verification.
- Create power verification planning and strategy
- Prepare power aware simulation environments
- Simulate and debug power aware simulations
You will bring
- Understanding of power techniques - e.g. CG, PG, MV, DVFS, MEM modes
- Understanding of power intent format - e.g. UPF or CPF
- Experience in power aware GLS
- Experience using formal for power verification
- RTL debugging with experience using Waveform debugging tools from one of the three largest EDA vendors
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