senior engineer- DV

Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Key Responsibilities

Job Responsibility

• Knowledge of Code coverage using features in existing simulators or stand-alone tools like Surecov, HDL score etc.

• Working on full chip verification and OVM/UVM Methodology, System Verilog is a must with 3+years of recent work experience, worked on passing test cases, test benches, Building environment.

• Knowledge of Functional coverage using HVL language features or assertions a plus.

• Should be ARM based SoC verification only. No need to mention tools.

• Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc.

Desired Skills & Experience:

• Experience level 3 to 5 years.

• Strong domain knowledge on one or more - PCIe,USB, Ethernet, ARM, AHB/AXI, AMBA, Networking, CPU, ARM, Graphics (DDR, PCIE, USB)

• Should have worked on SOC verification on at least one project with constrained random methodology (OVM/UVM).

• Good in concepts Code coverage and functional coverage.