Senior Engineer - ASIC Backend Synthesis

Grow with us

Join Ericsson’s cutting-edge journey to shape the future of 5G networks! As an Physical Synthesis Engineer, you’ll work on pioneering digital ASIC designs vital to Ericsson’s mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you’re passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you.

At Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you’ll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom!

We are hiring a Physical Synthesis Engineer to own the synthesis flow and constraint development on high-performance, low-power SoC designs. Your primary focus will be physical-aware synthesis, floorplan-driven netlist optimization, and QoR closure — while also contributing to static timing analysis (STA) signoff as well. You will work closely with RTL design, place-and-route, and DFT teams throughout the full design cycle.

What you will do:

Physical-Aware Synthesis (PAS)

• Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout timing and congestion surprises.

• Integrate synthesis with P&R tools for early physical feedback loops — congestion-aware optimization, placement-aware buffering, and pre-CTS timing.

• Collaborate with P&R engineers on DEF/floorplan hand-off; iterate on netlist quality to reduce downstream ECO effort.

• Perform flat and hierarchical synthesis for large designs; manage partitioning and interface timing budgets.

• Perform formal or equivalence check on the netlist at block or top level.

QoR & Optimization