Principal Engineer-Physical Design

Company Description

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

Job Summary:

We are seeking an experienced Senior Principal Engineer / Senior Manager – Physical Design Lead to lead the implementation and delivery of next-generation, high-performance SoC products built on advanced process technologies. This role will be responsible for driving the complete physical design execution of large-scale SoCs, from floorplanning through tape-out, while achieving aggressive performance, power, area, and schedule targets.

The ideal candidate will have a proven track record delivering complex 3nm and/or 5nm SoCs, with deep expertise in physical implementation of extremely high-speed designs incorporating large digital subsystems, high-speed SerDes interfaces, mixed-signal blocks, and advanced power management architectures.

Key Responsibilities:

• Lead the end-to-end physical design execution of large and complex SoCs from floorplanning through GDS signoff.

• Own implementation strategy, execution planning, risk management, and tape-out readiness.

• Drive floorplanning, power planning, placement, clock tree synthesis, routing, timing closure, signal integrity, IR/EM closure, and physical verification.