Micro-architecture and RTL Lead, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 10 years of experience in ASIC development with Verilog/SystemVerilog, VHDL.

• Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

• Experience in micro-architecture and design of IPs and subsystems in networking domain such as packet processing, bandwidth management, congestion control, etc.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience with programming languages (e.g., Python, C/C++ or Perl).

• Experience in SoC designs and integration flows.

• Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies.

• Knowledge of high performance and low power design techniques.