Manager / Senior Manager – Design Verification

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Meet the Team Join a dynamic Design Verification team responsible for delivering robust IP and SoC solutions across multiple product programs. We work closely with Design, Architecture, Firmware, Validation, and Program Management teams across global locations to ensure high-quality silicon delivery. Collaboration, innovation, technical excellence, and continuous improvement define our culture, making this an exciting opportunity to lead, grow, and make a significant impact.

About the Role

We are seeking an experienced Manager / Senior Manager – Design Verification to join our Silicon Engineering team in Hyderabad. In this role, you will lead and develop a high-performing verification team responsible for IP and SoC verification across multiple projects. You will drive verification planning, execution, closure, and on-time delivery while providing strong technical and people leadership. You will also collaborate with cross-functional and global teams, improve verification methodologies and automation, and champion the adoption of advanced verification techniques, AI-assisted workflows, and industry best practices. This is an excellent opportunity to lead complex verification programs, build scalable verification capabilities, and develop the next generation of engineering leaders.

Responsibilities

• Lead and develop a high-performing Design Verification team responsible for IP and SoC verification across multiple projects.

• Drive verification planning, execution, functional coverage closure, regression management, sign-off, and on-time delivery with high quality.

• Provide technical leadership in SystemVerilog, UVM, assertions, constrained-random verification, coverage-driven verification, and debug methodologies.