High Speed AMS - ASIC Engineering Technical Leader

Meet the Team

Cisco’s Silicon One Optics Group (S1O) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping S1O’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry.

You will work with Cisco's best-in-class Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures.

We seek an experienced High Speed AMS Design Engineer to lead full-chip electrical specifications and mixed-signal design for Cisco's silicon photonics driver integrated circuits supporting 100G/200G/400G per Lambda solutions. You will own high-speed datapath and low-speed control circuit design for receive and transmit paths in our next-generation silicon photonics modules.

Your Impact

- Provide technical leadership in analog/mixed-signal design for Cisco's next generation silicon photonics driver integrated circuits for 100G/200G/400G per Lambda solutions.

- Lead full-chip electrical specifications, circuit design, and verification test plans from concept through production, coordinating across electrical, optical, and product teams.

- Author mixed-signal datapath designs including photonics modulator drivers, serializers, PLLs, TIAs and control circuits while optimizing for power, performance, testability, and cost.

- Debug complex silicon and system-level issues during bring-up, and lab validation phases, driving yield enhancements and failure analysis.

- Mentor and guide analog, digital, and validation engineers while collaborating with architecture and product teams on verification and testability strategies.

Minimum Qualifications

- Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of high-speed AMS design experience