(CPU)L2 Cache Design Engineer – Micro-Architecture & Coherency
Qualcomm
Join Our High-Performance CPU Design Team! We are looking for passionate engineers to help shape the next generation of compute architectures. If you thrive on solving complex problems in cache design and coherency, this is your opportunity to make an impact.
Role Overview
As an L2 Cache Design Engineer, you will:
- Drive micro-architecture development for L2 cache subsystems, from concept to detailed specification.
- Implement and optimize cache coherency protocols for multi-core and multi-socket systems.
- Collaborate with architects, RTL designers, and verification teams to deliver high-quality, low-power designs.
- Analyze and improve performance, power, and area (PPA) trade-offs for cache structures.
- Support functional and performance verification, ensuring correctness and efficiency.
Key Responsibilities
- Develop micro-architecture specifications for L2 cache and related coherency logic.
- Own RTL design and refinement to meet timing, power, and reliability goals.
- Work closely with DV teams on coherency verification strategies.
- Participate in performance modeling and exploration for high-bandwidth cache systems.
- Contribute to design methodology improvements and automation.
Required Skills
- Strong knowledge of cache and memory subsystems, including L2 cache design principles.
- Expertise in cache coherency protocols (MESI/MOESI, directory-based schemes).
- Proficiency in SystemVerilog RTL, simulation, and debug tools.
- Familiarity with AMBA CHI/AXI protocols and interconnect design.
- Understanding of low-power design techniques and timing closure.
- Solid grasp of computer architecture fundamentals: pipeline design, hazard detection, ordering rules.
- Experience with scripting (Perl/Python) for design automation is a plus.
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