CPU EM/IR CAD Engineer

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

As a CPU EM/IR CAD Engineer, you will develop, support, and enhance power integrity and electromigration analysis tools and methodologies for high‑performance custom CPU designs. Your work will be critical in ensuring robust power delivery, long‑term reliability, and silicon correctness for industry‑leading CPUs across advanced technology nodes.

Roles and Responsibilities:

- Serve as an expert user of Synopsys RedHawk‑SC and/or Cadence Voltus for EM and power integrity analysis, with exposure to PNR, STA, and extraction tools and flows used in CPU implementation.

- Support and enhance static IR, dynamic IR, and electromigration (EM) flows at block‑level and subsystem‑level CPU designs.

- Provide technical guidance and feedback to CPU PDN and Physical Design teams on EMIR best practices, rules, and CPU‑specific methodologies.

- Troubleshoot and debug CPU‑specific EMIR challenges arising from high current density, frequency scaling, and aggressive PPA targets, and propose effective solutions.