ASIC Methodology, Flow and Integration Engineer

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are now looking for ASIC Flow and Integration Engineer to drive design methodology, automation, and integration for our High Speed IO team.

What you'll be doing:

As one of the primary methodology engineer, you’ll work across all NVIDIA-delivered projects, owning the integration process and collaborating with global teams to define and implement best-in-class methodologies. You’ll operate beyond RTL coding—building infrastructure and systems that are modular, reusable, and easily deployable across diverse silicon platforms. During the course of a project you would end up driving the following aspects of:

- Own the full-chip and block-level integration process across multiple NVIDIA SoC and GPU projects.

- Stitch together RTL units and ensure seamless connectivity, and hierarchy management.

- Define and evolve internal design methodologies to improve scalability, quality, and turnaround time.

- Build automation pipelines using Python/Perl to streamline integration, debug, and delivery.

- Develop modular and reusable systems that can be easily delivered and adapted across different SoC and GPU architectures.

- Collaborate extensively with RTL, verification, physical design, and architecture teams to ensure flow compatibility and design readiness.

- Drive full-chip debug efforts, connectivity, and functional issues across multiple hierarchies and technology nodes.

- Contribute to continuous improvement of internal standards and mentor engineers on flow usage and integration practices.

What we need to see:

- BS or B.Tech or MS or M.tech in EE, ECE, CS, or equivalent degree with 2+ years or more experience in design integration and methodologies for ASIC design.