ASIC Design Verification Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.

• 8 years of design verification experience.

• Experience verifying digital logic at RTL using SystemVerilog and UVM for ASICs.

• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, caches, Coherency, hierarchical memory subsystems, DDR/LPDDR).

Preferred qualifications:

• Master's degree in Electrical Engineering or Computer Science with 10 years of relevant work experience.

• Experience creating and using verification components and environments in a standard verification methodology such as UVM.

• Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture, LPDDR.

• Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification using Industry leading formal tools.

• Experience with GLS, low-power DV, and support of SOC DV.

• Experience in formal verification.