ASIC Design Engineer - RTL and Circuits
NVIDIA
We are now looking for a motivated ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.
NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!
What you'll be doing:
- Collaborate with cross-functional teams to define system-level architecture of mixed-signal chips for power delivery and power management solutions.
- Define micro-architecture and specifications of digital IP blocks to improve the power and performance of NVIDIA’s next generation GPUs
- Partner with RTL and Design Verification engineers to ensure delivery meets performance and quality expectations.
- Work with front-end teams to overlook correctness of the design (Lint/NA/CDC/Synthesis/DFT/LEC/STA)
- Partner and work with back-end team until chip tape-out.
- Work with firmware teams to define program flow and interface with digital IPs.
- Craft and develop behavioral models in RTL for mixed-signal blocks.
What we need to see:
- B.S. or MS degree in Electrical Engineering (or equivalent experience)
- 1+ years of proven experience and a background in logic design, Verilog and/or System-Verilog with a deep understanding of physical design and VLSI
- Experience with RTL development, Custom Digital Design, and Behavioral Circuit Modeling for mixed-signal blocks.
- Well-versed with Verilog/SystemVerilog
- Strong familiarity and experience with all stages of ASIC design flow including front end design and verification, DFT, and timing analysis
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