Staff Engineer, CPU Architectural Modeling & ISA Simulation

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

At Tenstorrent, we build open, state of the art compute for real workloads and real developers.

You will own CPU architectural modeling and ISA simulation strategy, shaping how our out-of-order RISC-V CPUs are modeled, validated, and checked against architectural intent, privileged architecture requirements, and system-visible correctness across the pre-silicon verification stack.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You bring 8+ years in CPU architectural modeling, ISA simulation, reference model development, CPU architectural verification, or closely related CPU validation work.

• You have strong experience building, extending, or validating functional models and simulators for CPU pipelines, ISA behavior, privileged architecture, and exception handling.

• You understand RISC-V ISA behavior, memory ordering, trap and interrupt flows, and high-performance out-of-order CPU microarchitecture in depth.

• You are comfortable debugging architectural mismatches using RTL, waveforms, logs, traces, reference models, and complex test scenarios across simulation and emulation.

• You communicate clearly across architecture, design, DV, emulation, compiler, and post-silicon teams.