Principal Analog Layout Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell Central Engineering (CE) develops Marvell's most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production. Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.

This is a rare foundational engineering opportunity as part of our strategic expansion into Southern California. You will help shape the technical DNA and culture of Marvell's San Diego design organization.

What You Can Expect

- Drawing layouts for schematics created by Circuit Design Engineers, using industry standard CAD tools, in deep sub-micron, FinFET technologies.

- Effectively communicate with Design Engineers to clarify and realize the layout requirements based on the schematic functions.

- Provide feedback to Circuit Design Engineers on any modifications to schematics after layouts are completed.

- Interact with Physical Verification (PV) team to analyze DRC, LVS, ANT, ERC, and EMIR results and achieve PV closure.

- Adhere to Marvell’s core behaviors and strive to continuously improve your skills as an Analog Layout Engineer.

- Experienced in Cadence “Virtuoso VXL” and/or Synopsys “Custom Compiler” layout tools.