Staff Physical Design Engineer

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

About the Role

Lattice Semiconductor is seeking a Staff Physical Design Engineer to join our Pune engineering center. In this role, you will own physical implementation of complex digital blocks and IP for our low-power FPGA products — from netlist to GDSII — working closely with RTL design, integration, and architecture teams to deliver first-pass silicon.

Responsibilities

• Own block-level physical design execution: floorplanning, power planning, placement, clock tree synthesis, routing, and timing closure

• Drive synthesis and place-and-route flows using industry-standard EDA tools (Synopsys Fusion Compiler / ICC2, Cadence Innovus, or equivalent)

• Perform static timing analysis and closure across PVT corners and modes

• Execute physical verification and sign-off: DRC, LVS, ERC, antenna, EM/IR analysis

• Implement low-power design techniques — UPF-based power intent, power gating, multi-Vt optimization

• Collaborate with RTL, DFT, and integration teams to resolve design convergence issues and support ECO cycles