Staff Engineer, Physical Design - Cores

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

About the Role --

At SiFive, we’re redefining the compute landscape with our industry-leading RISC-V compute platforms. As a Staff Physical Design Engineer (CPU Cores), you will own the physical implementation of critical, high-performance processor core blocks from RTL to GDSII. You will deliver high-frequency, power-efficient CPU designs on advanced and legacy process nodes. While your primary focus will be in physical design, we are looking for engineers capable of operating across design-abstraction layers. You will collaborate across architecture, RTL, and power teams. Leveraging a deep understanding of the processor pipeline and design goals, you will be instrumental in co-designing PPA (Power, Performance, Area) optimizations. This work directly enhances the frequency, area, and power-efficiency of our core IP.

Responsibilities - What you’ll do

- Own Core Implementation: Drive the physical design implementation for high-frequency CPU core blocks and execution pipelines, managing synthesis, place & route, and signoff.

- Engage in Cross-Abstraction-Layer Co-Design: Go beyond standard implementation by actively collaborating with Architecture/RTL/Power for PPA co-optimisation. Understand the CPU microarchitecture to identify logic-depth bottlenecks early and suggest RTL pipelining strategies or structural changes.