Staff Engineer, Physical Design
SiFive
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
About the Role
As a Staff Physical Design Engineer, you will be a key technical contributor driving the physical design implementation of our next-generation IPs. You will be responsible for translating complex RTL into high-performance implementation, ensuring architecture/design achieves its absolute peak physical potential.
We are looking for a true "full-stack" physical design engineer who is deeply curious about the logic they are building. You should be the type of engineer who thrives at the convergence of microarchitecture and physical layout, enjoying the challenge of analyzing how an architectural datapath choices affect congestion, how a memory floorplan impacts PPA, and how to push the boundaries of Power, Performance, and Area (PPA) through cross-functional collaboration.
Key Responsibilities - What you’ll do
- End-to-End Implementation: Drive the complete physical design flow (Synthesis, Floorplanning, P&R, Signoff) for major sub-systems and diverse IP blocks, ensuring they meet or exceed aggressive targets for PPA.
- Architectural & RTL Co-Optimization: Actively partner with RTL and Architecture teams from early-stage design to signoff. Identify physical and structural bottlenecks early—such as routing congestion in complex crossbars, dynamic power hot-spots in execution units, and interconnect span limits—and co-design microarchitectural or structural solutions to overcome them.
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