Staff EDA Engineer – RTL Front End Tools & Methodologies
Lattice Semiconductor
Lattice Overview
There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.
Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.
Job Description
Staff EDA Engineer – RTL Front‑End Tools & Methodologies
Experience
9–11 years (with 6+ years of deep, hands‑on experience in RTL front‑end EDA tools, flows, and methodologies)
Location
Pune, India – Non‑negotiable
Work Model
Hybrid with mandatory 4 days per week working from the Pune office
Job Summary
We are seeking a Staff EDA Engineer with strong expertise in RTL front‑end methodologies, power analysis, and simulation tool support. This role requires technical ownership and leadership in enabling scalable, high‑quality RTL flows, driving low‑power initiatives, building automation, and adopting Generative‑AI capabilities within EDA tools.
The ideal candidate will work closely with design, verification, CAD, and EDA vendor teams, contributing both to day‑to‑day project enablement and to long‑term front‑end EDA strategy. This is a hands‑on, high‑impact role requiring regular collaboration from the Pune site.
Key Responsibilities
- Act as technical owner for RTL front‑end EDA methodologies, including simulation, power analysis, and constraint validation.
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