Sr Staff Engineer, Power Integrity (PI), Signoff Lead

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

About the Role:

We are seeking a highly experienced Senior Staff Power Integrity Engineer to serve as the primary technical authority and owner for all IR drop and power delivery aspects of our high-speed CPUs. In this role, you will define sign-off criteria, drive advanced power analysis methodologies, and spearhead the automation of power and IR flows to ensure highly efficient, robust power delivery networks for high-performance compute architectures.

Key Responsibilities

- Technical Leadership: Act as the primary point of contact and subject matter expert for dynamic and static IR signoff criteria across the high-speed CPU design team.

- Power Delivery Architecture: Architect highly efficient, power-density-aware Power Grid (PG) designs and optimize bump maps based on rigorous power density requirements.

- IR Flow Automation: Spearhead the IR drop analysis flow. Collaborate closely with the Physical Design (PD) and Power teams to automate and streamline static and dynamic IR readouts.