Sr.Lead STA Engineer

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Overview:

As a Sr.Lead (STA) Engineer, you will be a key contributor to SoC level timing closure, working closely with RTL, CAD, DFT and physical design teams. You will drive timing analysis and closure for complex, multi‑GHz designs across block, cluster, and full‑chip hierarchies, ensuring aggressive frequency and power targets are met.

Roles and Responsibilities

• Work closely with RTL team to understand different protocols (DDR, PCIE, UCIE etc..), critical paths, and performance goals, and to define, implement, and validate timing constraints.
• Perform STA for high‑performance designs at block, cluster, and SoC/top‑level hierarchies across multiple modes, corners, and scenarios.
• Analyze timing on frequency‑critical paths and collaborate with RTL and DFT teams to drive logic and micro‑architectural fixes.
• Provide actionable timing feedback to block‑level and top‑level physical design engineers
• Generate and review timing ECOs (logic and physical) to close setup, hold, noise, and cross‑talk violations.