SoC Power Architect, Devices and Services, Silicon

Minimum qualifications:

• Bachelor's degree in Electronics or Computer Engineering or equivalent practical experience.

• 8 years of experience in ASIC power management or low power design methodology.

• Experience with ASIC low power flows and power management concepts.

Preferred qualifications:

• Master's degree in Electronics or Computer Engineering or equivalent practical experience.

• Experience with SoC/System-level power modeling and estimation, defining power targets, power roll-ups, power/voltage domains design and low power architectures/optimization techniques (e.g., clock gating, power gating, multi Vth, DVFS).

• Knowledge of the impact of software and architectural design decisions on system power and thermal behavior.

• Familiarity with PMIC, SMPS, LDO and power delivery networks.

• Excellent understanding of mobile SoC architectures and data flows, and experience with path-to-DDR IPs (e.g., Fabrics, System Cache, Memory Controller, DDRPHY, DRAM).