SoC DFT Technical Manager

Minimum qualifications:

• Bachelor's degree in Electrical, Computer Engineering or equivalent practical experience.

• 10 years of experience in SoC DFT architecture and design.

• 10 years of experience in DFT protocols including Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).

• 10 years of experience with industry-standard EDA tools such as Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus.

• 4 years of people management experience developing employees and leading multiple SoC projects from RTL architecture through to post-silicon validation.

• Experience in Tcl, Python, or Perl for developing automation flows.

Preferred qualifications:

• PhD in Electrical Engineering with a focus on VLSI testing, fault tolerance, or reliability.

• Experience with advanced technology nodes (5nm/3nm), 2.5D/3D-IC packaging, or high-speed I/O (SerDes/DDR) testing methodologies.

• Experience managing global technical teams and driving vendor engagement.

• Ability to drive cross-functional timing closure, power analysis, and IR-drop mitigation for high-frequency designs.