Silicon SoC Integration Design Lead, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 10 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel.

• 5 years of experience in micro-architecture and design of SoCs and subsystems.

• 4 years of experience in people management, developing employees.

• Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience in SoC designs and integration flows.

• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.

• Knowledge of high-performance and low power design techniques.