Silicon Micro-architecture and RTL Lead, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL).

• Experience in micro-architecture and design IPs and subsystems.

• Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:

• Experience with scripting languages (e.g., Python or Perl).

• Experience in SoC designs and integration flows.

• Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies..

• Knowledge of high-performance and low-power design techniques.