Silicon DFT Engineer III, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.

• 4 years of experience in the DFT , including implementation and DFT verification for the ASIC/SoC designs.

• Experience in DFT validation, including Phase-Locked Loop (PLL), sensors, Gate Level Simulations (GLS) simulation with timing, generating test cases, and debugging GLS.

• Experience in IEEE1149/1500/1687, CTL generation, MBIST, HSIOs, scan, Analog IPs, and Automatic Test Pattern Generation (ATPG).

• Experience with industry-standard DFT EDA tools.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.

• Experience with silicon process and technology nodes for high speed and low power consumption.

• Experience in post-silicon validation and debug.

• Experience in DFT and RTL