Senior Technical Architect

Perform end‑to‑end physical design flow:

Floorplanning Power planning (PG grid, IR) Placement & optimization CTS (Clock Tree Synthesis) Routing Post‑route optimization Achieve timing closure across all modes and corners Resolve DRC, LVS, ERC and signoff violations

Handle low‑power design techniques:

Multi‑Vt, Multi‑voltage (UPF) Power gating, clock gating

Perform physical verification and signoff:

STA (Primetime) SI / Crosstalk IR drop & EM analysis Work on advanced nodes (7nm, 5nm, 3nm or below)

Collaborate with:

RTL & Micro‑architecture teams DFT & Test engineers Foundry and CAD teams Debug complex timing, congestion, power, and variability issues Drive methodology improvements and automation (scripts/flows)

Key Responsibilities

1. To design and architect large-scale solutions, ensuring scalability, performance, and security.
2. To train and develop team so as to ensure that there is an adequate supply of trained manpower in the said technology and delivery risks are mitigated.
3. To continuously upskill with cutting-edge tech to deliver high-quality, future-proof solutions meeting client expectations and industry standards.
4. To leverage domain/tech expertise to gather client needs, deliver solutions, and craft a technology strategy aligned with business goals.

Skill Requirements null

Other Requirements

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