Senior System Integration and Validation Engineer

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first.

We are hiring a Senior Engineer to lead system validation, debug, and cross-functional alignment on one of our most consequential silicon programs. Your work will sit on the critical path of every flagship build, and the judgment you bring to ambiguous, multi-team failures is the difference between shipping on milestone and slipping! The two hardest, highest-leverage problems in this seat:

Find critical silicon and platform issues before they reach the customer — by shifting validation coverage left with system stress, PVT, and feature-interaction tests that catch escapes before software hardens. Your work shows up in DPPM, escape rate, and ramp confidence.

Build AI-enabled validation as a real capability, not a demo — by deploying debug, triage, root-cause hypothesis generation, and regression workflows with the evals and guardrails that make them trustworthy enough to gate production decisions.

What you’ll be doing:

Own end-to-end system validation of NVIDIA GPU, SoC, and platform programs — feature checks, PVT stress, system-stress campaigns at scale, and multi-unit fleet testing.

Lead debug of the hardest cross-stack issues — logic, signal integrity, power delivery, firmware, and software interaction — and drive them to root cause with reusable workarounds and productized fixes.

Develop test plans, scripts, and automation for next-generation chips ahead of physical builds, translating architecture, boot flows, high-speed I/O, and power and thermal dependencies into executable coverage.

Design and deploy AI-enabled debug and validation workflows used by the team — with explicit guardrails (evals, regression validation, false-positive handling) and measurable impact on cycle time, debug velocity, or escape rate.

Translate complex silicon and system risk into decision-ready options for technical and executive audiences — without padding or hand-waving.

Partner with globally distributed teams across silicon design, DFT, firmware, software, manufacturing, and platform engineering — including counterpart engineers in India and other major hubs.