Senior / Staff Design Verification Engineer

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

We are seeking a highly skilled and motivated Senior Design Verification Engineer with over 5 years of experience to join our silicon engineering team. In this role, you will play a critical part in ensuring the functional correctness of complex, next-generation SoCs/IPs. You will be responsible for the entire verification lifecycle—from scoping and test plan creation to architecture development, debugging, and achieving 100% coverage closure. The ideal candidate possesses rock-solid verification fundamentals, deep expertise in System Verilog (SV) and UVM, and a proven track record of delivering tape-out-ready designs.

Key Responsibilities

• Testplan Ownership: Review architectural and micro-architectural specifications to define, architect, and author comprehensive, feature-driven verification plans (testplans).

• Environment Development: Design, build, and maintain scalable, reusable, and robust constrained-random verification environments from scratch using SystemVerilog (SV) and the UVM methodology.