Job Details:Job Description: Role Overview We are looking for a strong architecture lead to define and drive architecture specifications for Unified Intel Chassis (UIC) IP components and subsystems. This role combines architecture definition with implementation awareness and performance ownership. The candidate will also work on platform-level performance, including building performance environments and driving closure in partnership with system architects and cross-functional teams.
The architecture must be power-optimized, highly scalable, and practical for implementation across multiple product generations.
Key Responsibilities
Author architecture specifications for Unified Intel Chassis IP components and subsystem integration.
Ensure architecture is implementation-aware, scalable, and power-optimized.
Drive platform performance analysis and closure, including bottleneck identification and optimization.
Build and enhance platform performance environments, models, and benchmarking flows.
Define and validate end-to-end QoS, arbitration, and routing strategies for high-bandwidth traffic.
Partner with system architects, RTL/design, verification, firmware/software, and performance teams to align architecture with product goals.
Define architecture trade-offs, assumptions, interfaces, and measurable success criteria.
Support debuggability, safety, reliability, and serviceability requirements in architecture definition.
UIC IP Scope
UIC Coherent and Non-Coherent Fabric
Protocol Adaptors for industry-standard protocols (AXI, CHI, CXL, UAL, etc.)
Cache Controller IP
MMU / IOMMU IP
Clock, Reset, and Power Management IP
Debug and Analytics IP
Security and Access Management IPQualifications:Minimum qualifications, you must possess the below minimum qualifications to be initially considered for this position.
B.Tech ,M.Tech or BS degree in a specialized field such as Computer Science, Electrical Engineering, or related discipline along with 6 or more years of relevant technical experience.
MS degree in a specialized field such as Computer Science, Electrical Engineering, or related discipline along with 4 or more years of relevant technical experience.
Strong experience in SoC IP architecture for high bandwidth interconnect and/or subsystem design.
1+ years of experience working with AMBA protocols, especially AXI, CHI, and APB.
Prior experience writing high-quality architecture specifications used by design and verification teams.
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Familiarly with AI tools to develop machine readable specification documents for spec2silicon fast and reliable execution
Excellent collaboration and communication skills across architecture and implementation teams Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Deep understanding of coherency concepts and CHI architecture.
Proven expertise in arbitration and routing algorithms, end-to-end QoS (Quality of Service), and high-bandwidth low latency, scalable designs.
Experience with fabric-based scalable platforms across multiple markets or generations.
Exposure to performance modelling, simulation, and data-driven architecture tuning.
In-depth understanding of cache architecture and memory management/address translation MMU, IOMMU.
Familiarity with security architecture and access control frameworks in SoC platforms.
DVFS and Distributed power management
Background in debug, safety, and RAS architecture. Job Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/AWork Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
