Senior Silicon Physical Design STA Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.

• 5 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.

• 5 years of experience with Static Timing Analysis (STA) convergence on blocks, Subsystem (SS) or SoC.

• Experience with System on a Chip (SoC) cycles.

• Experience in high-performance, high-frequency, and low-power designs.

Preferred qualifications:

• Master’s degree in Electrical Engineering.

• Experience in coding with System Verilog and scripting with Tool Command Language (TCL).

• Experience in Very-Large-Scale Integration (VLSI) design in SoC or experience with multiple-cycles of SoC in ASIC design.

• Experience in coding constraints and scripting with TCL.