Senior Silicon Digital Design Engineer, Core IP

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.

• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.

• Experience with ASIC design methodologies for clock domain checks and reset checks.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.

• Experience implementing machine learning accelerators or camera ISP image processing IP or other multimedia IPs such as display or video codec.

• Proficient in scripting languages, C/C++ programming and software design skills.

• Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.