Senior IP Verification Engineer(IOMMU-N)
SiFive
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Core Responsibilities:
- Verification Planning: Analyze architectural specifications to define verification strategies and create comprehensive test plans that outline test cases, checkers, and coverage goals.
- Testbench Development: Design and implement scalable, reusable, and constrained-random verification environments using System Verilog and UVM (Universal Verification Methodology).
- Stimulus & Constraint Generation: Write complex sequences and constrained-random tests to stress-test the IP across corner cases.
- Debugging: Perform deep-dive root cause analysis on RTL design failures and testbench issues using waveform viewers (e.g., Verdi, SimVision).
- Coverage Closure: Define and track functional and code coverage metrics. Write covergroups and coverpoints to ensure all architectural features have been exercised.
- Languages : System Verilog, Verilog, Python/Perl (scripting), C/C++
- Methodologies: UVM (highly preferred), OVM, or VMM
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