NVIDIA is seeking a Senior Formal Verification engineer for the Hardware Engineering team. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to tackle some of the most complex problems in computer science. It started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. This is our life’s work — to amplify human imagination and intelligence. And we have only scratched the surface of what we can accomplish when we apply our technology to it. We need passionate, hardworking, and creative people to help us take on some of these once-in-a-lifetime opportunities. This position offers the opportunity to have real impact in a progressive, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What you’ll be doing: Learning state-of-the-art formal verification methodologies Responsible for applying best-in-class formal methodologies on complex digital designs, IP blocks and SoCs Taking ownership of verifying a design by developing a robust test plan Executing it by working with the design team Coordinating with other verification team members for closure What we need to see: B.Tech./ M.Tech. in Electrical Engineering / Computer Science with 5+ years of experience Strong analytical skills to solve difficult problems Understanding of abstraction techniques for effective verification Hands-on experience with HDLs such as Verilog / System Verilog Ability to understand RTL quickly Understanding of temporal logic assertions