Senior Engineer, R2G Methodology and PD execution

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

The Role:

As a Senior Physical Design Engineer, you will be responsible for executing and optimizing the RTL-to-GDS implementation flow for our high-performance CPU cores. In this role, you will take ownership of block-level implementation and contribute to advanced design recipes to drive PPA (Power, Performance, Area) closure on leading-edge N3/N2 process nodes. This position focuses on high-quality technical execution, hands-on design closure, and utilizing automated, ML-enhanced methodologies to hit aggressive frequency and power targets within a highly collaborative team environment.

Key Responsibilities

- Flow Execution & Validation: Implement, validate, and maintain production-ready RTL-to-GDS recipes using Synopsys Fusion Compiler based on established methodology guidelines.

- Block Ownership: Take end-to-end implementation ownership of medium-sized CPU sub-blocks, driving them from RTL synthesis through to final GDS sign-off.

- PPA Optimization: Drive block-level PPA closure and contribute to hierarchical closure efforts, utilizing advanced techniques in timing-driven placement, CTS, and routing.