Senior Engineer - ASIC Verification

About this opportunity:

We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies.

As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork.

Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts.

Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide.

Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life.

Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development.

A collaborative and inclusive culture that values diversity and innovation.

You will do:

• Take part in the verification of designs, whether at the block or subsystem level.

• Participate in defining and implementing UVM-based test environments.

• Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans.