Senior Design Verification Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 8 years of experience verifying digital logic at RTL level using System Verilog and creating and using verification components and environments in standard verification methodology.

• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

• Experience creating and using verification components and environments in standard verification methodology.

• Experience verifying digital systems using standard IP.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience with industry-standard simulators, revision control systems, and regression systems.

• Experience in Artificial Intelligence/Machine Learning (AI/ML) accelerators or vector processing units.

• Experience in verification and debug of IP/subsystem/SoCs in the Networking domain such as packet processing, bandwidth management, congestion control desired.