Senior Design Verification Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.

• 8 years of experience with Design Verification.

• Experience verifying digital logic at RTL using SystemVerilog and UVM for ASICs.

Preferred qualifications:

• Master's degree in Electrical Engineering or Computer Science, or equivalent practical experience.

• Experience creating and using verification components and environments in a standard verification methodology such as UVM.

• Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture.

• Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification using Industry leading formal tools.

• Ability to collaborate cross-functionally and globally, fostering relationships and sharing insights to achieve company objectives.