Senior ASIC Verification Engineer
NVIDIA
NVIDIA is seeking an outstanding Senior ASIC Verification Engineer to verify the design and implementation of the world’s leading SoC's and GPU's. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing!
What you’ll be doing:
- As a Senior Verification Engineer at NVIDIA, you will be responsible for verifying the design, architecture and micro-architecture using advanced verification methodologies
- Define the verification scope, and contribute to the development of the verification infrastructure for memory subsystem units
- Verify firmware code, with specific attention on verifying hardware/firmware interactions
- Collaborate with architects, designers, software engineers across sites to accomplish your goals
What we need to see:
- Bachelors or Masters in Computer Science, Computer Engineering, Electrical Engineering or closely related degree (or equivalent experience)
- 5+ years of experience
- Experience with verification methodology, creating reusable verification components
- Knowledgeable in verification using random stimulus along with functional coverage and assertion-based verification methodologies
- Fluency in Object Oriented Programming with SystemVerilog
- Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB), and methodologies (UVM or equivalent)
- Your work displays a passion for debugging and strong problem solving skills
- Strong communication skills are required
Ways to stand out from the crowd:
- Prior verification experience related to high speed IO protocols, or memory coherence is a big plus
- Experience debugging embedded firmware code (C or RISCV Assembly)
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