Senior ASIC RTL Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.

• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field.

• Experience with a scripting language like Perl or Python.

• Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.

• Experience in one or more functional areas, such as coherent fabrics (e.g., AMBA CHI/AXI), memory controllers (e.g., LPDDR5, DDR5), or I/O controllers (e.g., PCIe, CXL).

• Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.).

• Knowledge of memory compression, fabric, coherence, cache, or DRAM.