Principal Digital Design Engineer

Key Responsibilities

• Design and develop RTL (Register Transfer Level) code using Verilog/SystemVerilog/VHDL

• Architect and implement complex digital blocks and subsystems

• Perform functional verification using simulation tools and methodologies (UVM/OVM)

• Develop and execute testbenches and validation plans

• Perform logic synthesis, timing analysis, and area optimization

• Debug and troubleshoot design issues at RTL, gate, and silicon levels

• Collaborate with verification, physical design, and firmware teams

• Ensure designs meet power, performance, and area (PPA) targets

• Participate in design reviews, code reviews, and technical discussions

• Work with EDA tools for design implementation and validation

• Support post-silicon validation and bring-up activities

- Strong proficiency in:

• Verilog / SystemVerilog / VHDL

- Experience with:

• RTL design and simulation tools (ModelSim, VCS, Xcelium)