Principal Design Verification Engineer – CPU Core LSU
SiFive
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
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About the Role
SiFive is looking for a Principal Design Verification Engineer to lead verification strategy and execution for the CPU Core Load-Store Unit in a high-performance out-of-order core.
This is a principal tech-lead role for an engineer who can define architecture-aware verification strategy, identify the highest-risk microarchitectural issues early, and solve the most difficult LSU verification problems spanning load/store ordering, hazard handling, cache coherency, and memory consistency.
The role requires close partnership with architecture, RTL, formal, performance, and verification teams to ensure design intent is captured correctly, debugability is considered early, and signoff quality is achieved with scalable methodology and strong technical judgment.
Responsibilities
- Lead verification strategy for the CPU Core LSU, including block-level and core-level planning, execution, debug, coverage analysis, and closure.
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